1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device which can save processed data in an integrated thin film magnetic memory element when power is turned off.
2. Description of the Background Art
In recent years, large-scale circuits can be integrated in a semiconductor device, and a system LSI (large-scale integrated circuit), in which a logic circuit and a bulk memory is integrated on one chip, has been developed. In such a system LSI, a logic circuit unit and a memory unit transmit and receive information such as address, command and data via a prescribed port.
With the objective of attaining higher performance, a gate oxide film of a transistor has been made thinner, and a gate length of a transistor has been reduced. With such a thinner gate oxide film, a gate leak current further increases. Reduction of the gate length also causes an increase in a leak current between source and drain of the transistor in an off-state.
One of solutions for the increase in the leak current is to turn off a power supply voltage during standby. When the power supply voltage is turned off, however, data of a flip-flop within a logic circuit or a volatile memory will be lost. Therefore, when the power supply voltage is turned off to reduce current consumption, the data is previously saved in a memory for saving, which is separately arranged on a printed-circuit board or the like on which the system LSI is mounted. An example of the memory for saving includes a flash EEPROM (electrically erasable programmable read only memory).
As a conventional semiconductor device, a semiconductor device is proposed in which non-volatility can be implemented while keeping a high speed property of a static memory (SRAM) (for example, see FIG. 1 on pages 3–4 in Japanese Patent Laying-Open No. 7-226088).
In this technique, a flip-flop is formed with two transistors, and two selection transistors are connected to the two transistors to form an SRAM memory cell unit. In addition, a non-volatile memory cell unit storing a state of the SRAM memory cell unit is formed with two non-volatile transistors each including two gates, that is, a floating gate and a control gate, and having a drain connected to a power supply line. The high speed property of the SRAM and non-volatility of an EPROM, a Flash-EPROM or the like can concurrently be implemented by connecting the non-volatile memory cell unit to the SRAM memory cell unit.
The flash EEPROM or the like which writes data to the floating gate, however, needs a time period of several milliseconds for a writing stage. Because of this very long time period, much processing time is required before the power supply voltage is turned off. As a result, a transition time to a standby mode for reducing current consumption will be late.
In addition, as the flash EEPROM also takes a relatively long time to read data, a long time period is needed to read data and return the data of the volatile memory or flip-flop to its original state after the power is reset. Thus, it also takes a long time to activate the device.
Further, it is uneconomical to provide a memory for temporary saving on an external printed-circuit board, because the number of elements in the whole system as well as an area of the external printed-circuit board increase.